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www.fairchildsemi.com pentium is a registered trademark of intel corporation. athlon is a registered trademark of amd. programmable active droop is a trademark of fairchild semiconductor. rev. 1.0.2 5/13/02 features programmable output from 1.100v to 1.850v in 25mv steps using an integrated 5-bit dac two interleaved synchronous phases per ic for maximum performance up to 4 phase power system built-in current sharing between phases and between ics frequency and phase synchronization between ics remote sense and programmable active droop high precision voltage reference high speed transient response programmable frequency from 200khz to 2mhz adaptive delay gate switching integrated high-current gate drivers integrated power good, ov, uv, enable/soft start functions drives n-channel mosfets operation optimized for 12v operation high ef?iency mode at light load overcurrent protection using mosfet sensing 28 pin tssop package applications power supply for pentium iv power supply for athlon power supply for ultrasparc vrm for pentium iv processor programmable step-down power supply description the FAN5094 is a synchronous multi-phase dc-dc controller ic which provides a highly accurate, programmable output voltage for all high-performance processors. two interleaved synchronous buck regulator phases with built-in current sharing operate 180 out of phase to provide the fast transient response needed to satisfy high current applications while minimizing external components. FAN5094s can be paralleled while maintaining both frequency and phase synchronization and ensuring current sharing in a high-power system. the FAN5094 features remote voltage sensing, programmable active droop ? and advanced response for optimal converter transient response with minimum output capacitance. it has integrated high-current gate drivers with adaptive delay gate switching, eliminating the need for external drive devices. these make it possible to create power supplies running at a switching frequency as high as 4mhz, for ultra-high density. the FAN5094 uses a 5-bit d/a converter to program the output voltage from 1.100v to 1.850v in 25mv steps with an accuracy of 0.5%. the FAN5094 uses a high level of integration to deliver load currents in excess of 150a from a 12v source with minimal external circuitry. the FAN5094 also offers integrated functions including power good, output enable/soft start, under-voltage lockout, over- voltage protection, and current limiting with independent current sense on each phase. it is available in a 28-pin tssop package. block diagram +12v +12v +12v +12v FAN5094 vfb processor phase clk ishr + FAN5094 vfb phase clk ishr vfb + FAN5094 multi-phase interleaved buck converter
FAN5094 product specification 2 rev. 1.0.2 5/13/02 pin assignments pin de?itions pin number pin name pin function description 1-5 vid0-4 voltage identification code inputs. these open collector/ttl compatible inputs will program the output voltage over the ranges specified in table 1. 6 clk clock. when phase is high, this pin puts out a clock signal synchronized 180 out of phase with the internal master clock. when phase is low, this pin is an input for a synchronizing clock signal. 7 bypass 5v rail. bypass this pin with a 0.1 f ceramic capacitor to agnd. 8 agnd analog ground. return path for low power analog circuitry. this pin should be connected to a low impedance system ground plane to minimize ground loops. 9 ldrvb low side fet driver for b. connect this pin to the gate of an n-channel mosfet for synchronous operation. the trace from this pin to the mosfet gate should be <0.5? 10 gndb ground b. ground-side current sense pin. connect directly to low-side mosfet source, or to sense resistor ground. 11 isnsb current sense b. sensor side of current sense. attach to low-side mosfet drain, or to source side of sense resistor. 12 swb high side driver source and low side driver drain switching node b. gate drive return for high side mosfet, and negative input for low-side mosfet current sense. 13 hdrvb high side fet driver b. connect this pin to the gate of an n-channel mosfet. the trace from this pin to the mosfet gate should be <0.5? 14 bootb bootstrap b. input supply for high-side mosfet. 15 boota bootstrap a. input supply for high-side mosfet. 16 hdrva high side fet driver a. connect this pin to the gate of an n-channel mosfet. the trace from this pin to the mosfet gate should be <0.5? 17 swa high side driver source and low side driver drain switching node a. gate drive return for high side mosfet, and negative input for low-side mosfet current sense. 18 isnsa current sense a. sensor side of current sense. attach to low-side mosfet drain, or to source side of sense resistor. FAN5094 vid0 vid1 vid2 vid3 vid4 bypass agnd clk ldrvb gndb isnsb swb vfb rt enable/ss droop/e* ishr phase pwrgd vcc ldrva gnda isnsa swa 1 2 3 4 5 6 7 8 9 10 11 12 hdrvb bootb hdrva boota 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
product specification FAN5094 rev. 1.0.2 5/13/02 3 absolute maximum ratings 19 gnda ground a. ground-side current sense pin. connect directly to low-side mosfet source, or to sense resistor ground. 20 ldrva low side fet driver for a. connect this pin to the gate of an n-channel mosfet for synchronous operation. the trace from this pin to the mosfet gate should be <0.5 . 21 vcc vcc. internal ic supply. connect to system 12v supply, and decouple with a 0.1 f ceramic capacitor. 22 pwrgd power good flag. an open collector output that will be logic low if the output voltage is not within +/-5% of the nominal output voltage setpoint. 23 phase phase control. connecting this pin to bypass causes a synchronized clock signal to appear on clk. connecting this pin to ground allows the clk pin to accept a clock signal for synchronization. 24 ishr current share. connecting this pin to the ishr pin of another FAN5094 enables current sharing. 25 droop/e* droop control/e*-mode control. a resistor from this pin to ground sets the amount of droop by controlling the gain of the current sense amplifier. connecting this pin to bypass turns off phase a. 26 enable/ss output enable. a logic low on this pin will disable the output. an internal current source allows for open collector control. this pin also doubles as soft start. 27 rt frequency set. a resistor from this pin to ground sets the switching frequency. see apps section. 28 vfb voltage feedback. connect to the desired regulation point at the output of the converter. parameter min. typ. max. units supply voltage vcc 15 v supply voltages boota, bootb 22 v voltage identification code inputs, vid0-vid4 6 v vfb, enable/ss, pwrgd, phase, clk 6 v sw, isns -3 15 v pgnda, pgndb to agnd -0.5 0.5 v gate drive current, peak pulse 3 a junction temperature, t j -55 150 c storage temperature -65 150 c lead soldering temperature, 10 seconds 300 c thermal resistance junction-to-case, ja 16 c/w pin de nitions (continued) pin number pin name pin function description
FAN5094 product specification 4 rev. 1.0.2 5/13/02 recommended operating conditions parameter conditions min. typ. max. units output driver supply, boot see figure 1 16 17 v vcc 10.8 12 13.2 v input logic high 2.0 v input logic low 0.8 v ambient operating temperature 0 70 c electrical speci cations (v cc = 12v, v out = 1.500v, and t a = +25 c using circuit in figure 1, unless otherwise noted.) the ? denotes speci cations which apply over the full operating temperature range. parameter conditions min. typ. max. units output voltage see table i ? 1.100 1.850 v output current 60 a internal reference voltage 1.4925 1.5000 1.5075 v initial voltage setpoint i load = 0.8a 1.488 1.500 1.512 v output temperature drift t a = 0 to 70 c+5mv line regulation v in = 11.4v to 12.6v ? +130 v droop 3 i load = 0.8a to i max -90 -100 -110 mv programmable droop range r droop = tbd to tbd -10 0 %v out total output variation, steady state 1 i load = 0.8a to i max ? 1.430 1.570 v total output variation, transient 2 i load = 0.8a to i max ? 1.430 1.570 v response time ? v out = 10mv 100 nsec gate drive on-resistance 1.0 ? upper drive low voltage v hdrv v sw at i sink = 10a 0.2 v upper drive high voltage v boot v hdrv at i source = 10a 0.5 v lower drive low voltage i sink = 10a 0.2 v lower drive high voltage v cc v ldrv at i source = 10a 0.5 v output driver rise & fall time see figure 2 20 nsec current mismatch r ds,on (a) = r ds,on (b) 5 % output overvoltage detect ? 2.1 2.3 v efficiency i load = i max , i load = 2a, e*-mode enabled 85 70 % oscillator frequency rt = 41.2k ?? 450 600 750 khz oscillator range rt = 125k ? to 12.5k ? 200 2000 khz maximum duty cycle rt = 125k ? 90 % minimum ldrv on-time rt=12.5k ? 330 nsec input low current, vid pins v vid = 0.4v 50 a soft start current 10 a enable threshold on off 0.4 1.0 v bypass voltage 4.75 5 5.25 v bypass capacitor 220 1000 nf
product specification FAN5094 rev. 1.0.2 5/13/02 5 notes: 1. steady state voltage regulation includes initial voltage setpoint, output ripple and output temperature drift and is measured at the converter? vfb sense point. 2. as measured at the converter? vfb sense point. for motherboard applications, the pcb layout should exhibit no more than 0.2m ? trace resistance between the converter? output capacitors and the cpu. remote sensing should be used for optimal performance. 3. using the vfb pin for remote sensing of the converter? output at the load, the converter will be in compliance with intel? vrm 9.0 specification of +70, -70mv. pwrgd threshold logic low, minimum logic low, maximum ? ? 85 108 88 111 92 115 %v out pwrgd hysteresis 20 mv pwrgd output voltage i sink = 4ma 0.4 v pwrgd delay high low 500 ?ec 12v uvlo ? 8.5 9.5 10.5 v uvlo hysteresis 1.0 v 12v supply current hdrv and ldrv open 20 ma over temperature shutdown 150 ? over temperature hysteresis 25 ? electrical speci?ations (continued) (v cc = 12v, v out = 1.500v, and t a = +25? using circuit in figure 1, unless otherwise noted.) the ? denotes speci?ations which apply over the full operating temperature range. parameter conditions min. typ. max. units
FAN5094 product specification 6 rev. 1.0.2 5/13/02 note: 1. 0 = vid pin is tied to gnd. 1 = vid pin is pulled up to 5v. table 1. output voltage programming codes vid4 vid3 vid2 vid1 vid0 v out to cpu 11111off 11110 1.100v 11101 1.125v 11100 1.150v 11011 1.175v 11010 1.200v 11001 1.225v 11000 1.250v 10111 1.275v 10110 1.300v 10101 1.325v 10100 1.350v 10011 1.375v 10010 1.400v 10001 1.425v 10000 1.450v 01111 1.475v 01110 1.500v 01101 1.525v 01100 1.550v 01011 1.575v 01010 1.600v 01001 1.625v 01000 1.650v 00111 1.675v 00110 1.700v 00101 1.725v 00100 1.750v 00011 1.775v 00010 1.800v 00001 1.825v 00000 1.850v
product specification FAN5094 rev. 1.0.2 5/13/02 7 internal block diagram 2 3 26 vid0 13 11 16 15 20 19 28 - + - + master clock digital control power good 5-bit dac vid1 vid2 vid3 vid4 14 5 +12v pwrgd - + enable/ss vo agnd 8 ishr 24 droop/e* 21 7 +12v 18 17 5v reg 2 bypass 27 f/2 f/2 23 6 phase clk +12v +12v 14 9 10 25 +12v digital control - + - + 22 12
FAN5094 product specification 8 rev. 1.0.2 5/13/02 typical operating characteristics (v cc = 12v, and t a = +25 c using circuit in figure 1 , unless otherwise noted.) efficiency vs. output current 88 0 1020304050 60 86 84 82 80 78 76 74 72 70 68 66 64 output current (a) efficiency (%) v out = 1.550v v out = 1.850v v out (50mv / div) transient response, 50a to 0.5a 1.590v 1.550v 1.480v time (20 s/division) 10v/division high-side gate drives, normal operation transient response, 0.5a to 50a 1.590v 1.550v 1.480v v out (50mv / div) time (20 s/division) time (500ns/division) 10v/division high-side gate drives, e*-mode time (500ns/division)
product specification FAN5094 rev. 1.0.2 5/13/02 9 typical operating characteristics (continued) 10mv/division output ripple voltage time (1 s/division) 5v/division gate drive rise time time (50ns/division) 10v/division 5v/division adaptive gate delay time (50ns/division) 5v/division 50mv/division power good during dynamic voltage adjustment time (200 s/division) 5a/division current sharing between inductors time (500ns/division) 5v/division gate drive fall time time (10ns/division)
FAN5094 product specification 10 rev. 1.0.2 5/13/02 typical operating characteristics (continued) 180 160 140 120 100 80 60 40 20 0 5 0 101520253035404550 r droop (k ? ) droop vs. r droop , rt = 43k ? droop (mv) v out temperature variation temperature ( c) 1.501 1.500 1.499 1.498 1.497 1.496 1.495 1.494 0 25 70 100 v ou t (v)
product specification FAN5094 rev. 1.0.2 5/13/02 11 application circuit figure 1. three-phase application circuit for 65a willamette processor +5v vo 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 u1 FAN5094 +12v +5v +12v vid4 vid3 vid2 vid1 vid0 enable/ss c5 d3 d2 c4 c3 pwrgd +12v +12v +12v l1 (optional) c in r6 q1 r5 c2 +12v a b q2 c1 l2 c out l3 r7 r4 r1 d1 q4 q3 r8 r2 r3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 u2 FAN5094 +12v c7 +12v r13 q5 r12 c6 a b q6 l4 r11 r9 r10
FAN5094 product specification 12 rev. 1.0.2 5/13/02 table 2. FAN5094 application bill of materials for figure 1 notes: 1. inductor l1 is recommended to isolate the 12v input supply from noise generated by the mosfet switching. l1 may be omitted if desired. 2. for a spreadsheet on mosfet selections, refer to applications bulletin ab-8. reference manufacturer part # quantity description requirements/ comments c1, c3-5, c7 panasonic ecu-v1h104zfx 5 100nf, 50v capacitor c2, c6 any 2 1f ceramic capacitor c in rubycon 16mbz1500m 2 1500 f, 16v electrolytic i rms = 5.4a @ 65 c c out rubycon 6.3mbz2200m 5 2200 f, 6.3v electrolytic esr 13m ? d1-3 fairchild mbr0520 3 0.5a, 20v schottky diode l1 coiltronics dr127-1r5 optional 1.5 h, 14a inductor dcr ~ 3m ? see note 1. l2-4 coiltronics dr127-r47 3 470nh, 19a inductor dcr ~ 2m ? q1, q3, q5 fairchild fdb6035al 3 n-channel mosfet r ds(on) = 17m ? @ v gs = 4.5v q2, q4, q6 fairchild fdb6676s 3 n-channel mosfet with schottky r ds(on) = 6.5m ? @ v gs = 10v r1 any 1 10k ? r2, r9 any 2 24.9k ? r3, r10 any 2 2k ? r4, r11 any 2 10 ? r5-8, r12-13 any 6 4.7 ? u1-2 fairchild FAN5094m 2 dc/dc controller
product specification FAN5094 rev. 1.0.2 5/13/02 13 figure 2. four-phase application circuit for 81a northwood processor +5v vo 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 u1 FAN5094 +12v +5v +12v vid4 vid3 vid2 vid1 vid0 enable/ss c5 d3 d2 c4 c3 pwrgd +12v +12v +12v l1 (optional) c in r6 q1 r5 c2 +12v a b q2 c1 l2 c out l3 r7 r4 r1 d1 q4 q3 r8 r2 r3 l5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 u2 FAN5094 +12v c7 +12v r13 q5 r12 c6 a b q6 l4 r11 r9 r10 +12v r15 q7 r14 q8
FAN5094 product specification 14 rev. 1.0.2 5/13/02 table 3. FAN5094 application bill of materials for figure 2 notes: 1. inductor l1 is recommended to isolate the 12v input supply from noise generated by the mosfet switching. l1 may be omitted if desired. 2. for a spreadsheet on mosfet selections, refer to applications bulletin ab-8. test parameters figure 3. output drive timing diagram reference manufacturer part # quantity description requirements/comments c1, c3-5, c7 panasonic ecu-v1h104zfx 5 100nf, 50v capacitor c2, c6 any 2 1f ceramic capacitor c in rubycon 16mbz1500m 2 1500f, 16v electrolytic i rms = 5.4a @ 65 c c out rubycon 6.3mbz2200m 9 2200f, 6.3v electrolytic esr 13m ? d1-3 fairchild mbr0520 3 0.5a, 20v schottky diode l1 coiltronics dr127-1r5 optional 1.5h, 14a inductor dcr ~ 3m ?. see note 1. l2-5 coiltronics dr127-r47 4 470nh, 19a inductor dcr ~ 2m ? q1, q3, q5, q7 fairchild fdb6035al 4 n-channel mosfet r ds(on) = 17m ? @ v gs = 4.5v q2, q4, q6, q8 fairchild fdb6676s 4 n-channel mosfet with schottky r ds(on) = 6.5m ? @ v gs = 10v r1 any 1 10k ? r2, r9 any 2 24.9k ? r3, r10 any 2 2k ? r4, r11 any 2 10 ? r5-8, r12-15 any 8 4.7 ? u1-u2 fairchild FAN5094m 1 dc/dc controller t r t f t dt t dt hidrv lodrv 2v 2v 10% 2v 90% 90% 2v 10%
product specification FAN5094 rev. 1.0.2 5/13/02 15 application information operation the FAN5094 controller the FAN5094 is a programmable synchronous multi-phase dc-dc controller ic. when designed around the appropriate external components, the FAN5094 can be con?ured to deliver more than 100a of output current, as appropriate for the new generation of high-current processors. the FAN5094 functions as a ?ed frequency pwm step down regulator, with a high ef?iency mode (e*) at light load. main control loop refer to the FAN5094 block diagram on page 7. the FAN5094 consists of two interleaved synchronous buck con- verters, implemented with summing-mode control. each phase has its own current feedback, and there is a common voltage feedback. the two buck converters controlled by the FAN5094 are interleaved, that is, they run 180 out of phase with each other. this minimizes the rms input ripple current, mini- mizing the number of input capacitors required. it also doubles the effective switching frequency, improving transient response. the FAN5094 implements ?umming mode control? which is different from both classical voltage-mode and current- mode control. it provides superior performance to either by allowing a large converter bandwidth over a wide range of output loads and external components. the control loop of the regulator contains two main sections: the analog control block and the digital control block. the analog section consists of signal conditioning ampli?rs feeding into a comparator which provides the input to the digital control block. the signal conditioning section accepts inputs from a current sensor and a voltage sensor, with the voltage sensor being common to both phases, and the current sensor separate for each. the voltage sensor ampli?s the difference between the vfb signal and the reference voltage from the dac and presents the output to each of the two comparators. the current control path for each phase takes the difference between its pgnd and sw pins when the low-side mosfet is on, reproducing the voltage across the mosfet and thus the input current; it presents the resulting signal to the same input of its summing ampli?r, adding its signal to the voltage ampli?rs with a certain gain. these two signals are thus summed together. this sum is then pre- sented to a comparator looking at the oscillator ramp, which provides the main pwm control signal to the digital control block. the oscillator ramps are 180 out of phase with each other, so that the two phases are on alternately. the digital control block takes the analog comparator input to provide the appropriate pulses to the hdrv and ldrv output pins for each phase. these outputs control the exter- nal power mosfets. remote voltage sense the FAN5094 has true remote voltage sense capability, elim- inating errors due to trace resistance. to utilize remote sense, the vfb and agnd pins should be connected as a kelvin trace pair to the point of regulation, such as the processor pins. the converter will maintain the voltage in regulation at that point. care is required in layout of these grounds; see the layout guidelines in this datasheet. high current output drivers the FAN5094 contains four high current output drivers that utilize mosfets in a push-pull con?uration. the drivers for the high-side mosfets use the boot pin for input power and the sw pin for return. the drivers for the low-side mosfets use the vcc pin for input power and the pgnd pin for return. typically, the boot pin will use a charge pump as shown in figures 1?. note that the boot and vcc pins are separated from the chips internal power and ground, bypass and agnd, for switching noise immunity. adaptive delay gate drive the FAN5094 embodies an advanced design that ensures minimum mosfet transition times while eliminating shoot-through current. it senses the state of the mosfets and adjusts the gate drive adaptively to ensure that they are never on simultaneously. when the high-side mosfet turns off, the voltage on its source begins to fall. when the voltage there reaches approximately 2.5v, the low-side mosfets gate drive is applied with approximately 50nsec delay. when the low-side mosfet turns off, the voltage at the ldrv pin is sensed. when it drops below approximately 2v, the high- side mosfets gate drive is applied. maximum duty cycle in order to ensure that the current-sensing and charge- pumping work, the FAN5094 guarantees that the low-side mosfet will be on a certain portion of each period. for low frequencies, this occurs as a maximum duty cycle of approxi- mately 90%. thus at 500khz, with a period of 2?ec, the low-side will be on at least 2?ec ?10% = 200nsec. at higher frequencies, this time might fall so low as to be ineffective. the FAN5094 guarantees a minimum low-side on-time of approximately 330nsec, regardless of what duty cycle this corresponds to. current sensing the FAN5094 has two independent current sensors, one for each phase. current sensing is accomplished by measuring the source-to-drain voltage of the low-side mosfet during its on-time. each phase has its own power ground pin, to per- mit the phases to be placed in different locations without affecting measurement accuracy. for best results, it is impor- tant to connect the pgnd and sw pins for each phase as a kelvin trace pair directly to the source and drain, respec-
FAN5094 product specification 16 rev. 1.0.2 5/13/02 tively, of the appropriate low-side mosfet. care is required in the layout of these grounds; see the layout guidelines in this datasheet. current sharing the two independent current sensors of the FAN5094 operate with their independent current control loops to guarantee that the two phases each deliver half of the total output current. the only mismatch between the two phases occurs if there is a mismatch between the r ds,on of the low-side mosfets. in normal usage, two FAN5094s will be operated in parallel. by connecting the ishr pins together, the two error amps of the two ics will be forced to operate at exactly the same duty cycle, thus ensuring very close matching of the currents of all four phases. short circuit current characteristics the FAN5094 short circuit current characteristic includes a function that protects the dc-dc converter from damage in the event of a short circuit. the short circuit limit is given by the formula per phase. precision current sensing the tolerances associated with the use of mosfet current sensing can be circumvented by the use of a current sense resistor. light load ef ciency at light load, the FAN5094 uses a number of techniques to improve ef?iency. because a synchronous buck converter is two quadrant, able to both source and sink current, during light load the inductor current will ?w away from the out- put and towards the input during a portion of the switching cycle. this reverse current ?w is detected by the FAN5094 as a positive voltage appearing on the low-side mosfet during its on-time. when reverse current ?w is detected, the low-side mosfet is turned off for the rest of the cycle, and the current instead ?ws through the body diode of the high-side mosfet, returning the power to the source. this technique substantially enhances light load ef?iency. e*-mode in addition, further enhancement in ef?iency can be obtained by putting the FAN5094 into e*-mode. when the droop pin is pulled to the 5v bypass voltage, the a?phase of the FAN5094 is completely turned off, reducing in half the amount of gate charge power being consumed. e*-mode can be implemented with the circuit shown in figure 4: figure 4. implementing e*-mode control note that the charge pump for the hidrvs should be based on the ??phase of the FAN5094, since the a?phase is off in e*-mode. internal voltage reference the reference included in the FAN5094 is a precision band- gap voltage reference. its internal resistors are precisely trimmed to provide a near zero temperature coef?ient (tc). based on the reference is the output from an integrated 5-bit dac. the dac monitors the 5 voltage identi?ation pins, vid0-4, and scales the reference voltage from 1.100v to 1.850v in 25mv steps. bypass reference the internal logic of the FAN5094 runs on 5v. to permit the ic to run with 12v only, it produces 5v internally with a linear regulator, whose output is present on the bypass pin. this pin should be bypassed with a 1? capacitor for noise suppression. the bypass pin should not have any external load attached to it. dynamic voltage adjustment the FAN5094 has internal pullups on its vid lines. external pullups should not be used. the FAN5094 can have its output voltage dynamically adjusted to accommodate low power modes. the designer must ensure that the transitions on the vid lines all occur simultaneously (within less than 500 nsec) to avoid false codes generating undesired output voltages. the power good ?g tracks the vid codes, but has a 500?ec delay transitioning from high to low; this is long enough to ensure that there will not be any glitches during dynamic voltage adjustment. power good (pwrgd) the FAN5094 power good function is designed in accor- dance with the pentium iv dc-dc converter speci?ations and provides a continuous voltage monitor on the vfb pin. the circuit compares the vfb signal to the vref voltage and outputs an active-low interrupt signal to the cpu should the power supply voltage deviate more than +15%/-8% of its nominal setpoint. the output is guaranteed open-collector high when the power supply voltage is within +8%/-15% of its nominal setpoint. the power good ?g provides no control functions to the FAN5094. i sc 6v 10 r ? ds on , ------------------------------- - = bypass 10k ? 10k ? 10k ? 2n2222 2n2907 r droop FAN5094 pin25 hi = e*- mode on
product specification FAN5094 rev. 1.0.2 5/13/02 17 output enable/soft start (enable/ss) the FAN5094 will accept an open collector/ttl signal for controlling the output voltage. the low state disables the output voltage. when disabled, the pwrgd output is in the low state. even if an enable is not required in the circuit, this pin should have attached a capacitor (typically 100nf) to soft- start the switching. a softstart capacitor may be approxi- mately chosen by the formula: however, c must be 100nf. oscillator the FAN5094 oscillator section runs at a frequency deter- mined by a resistor from the rt pin to ground according to the formula the oscillator generates two square waves, 180?out of phase with each other. one is used internally, the other is sent to a second FAN5094 on the clk pin. the square wave generates two internal sawtooth ramps, each at one-half the square wave frequency, and running 180 out of phase with each other. these ramps cause the turn-on time of the two phases to be phased apart and the four phases to be 90?apart each. the oscillator frequency of the FAN5094 can be programmed from 400khz to 4mhz with each phase running at 100khz to 1mhz, respectively. selection of a frequency will depend on various system performance criteria, with higher frequency resulting in smaller components but lower ef?iency. programmable active droop the FAN5094 features programmable active droop: as the output current increases, the output voltage drops propor- tionately an amount that can be programmed with an exter- nal resistor. this feature is offered in order to allow maximum headroom for transient response of the converter. the current is sensed losslessly by measuring the voltage across the low-side mosfet during its on time. consult the section on current sensing for details. note that this method makes the droop dependent on the temperature and initial tolerance of the mosfet, and the droop must be calculated taking account of these tolerances. given a maximum load current, the amount of droop can be programmed with a resistor to ground on the droop pin, according to the formula with v droop the desired droop voltage, rt the oscillator resistor, i max the load current at which the droop is desired, n the number of phases, and r ds, on the on-state resistance of one phases low-side mosfet. typical response time of the FAN5094 to an output voltage change is 100nsec. important note! the oscillator frequency must be selected before selecting the droop resistor, because the value of rt is used in the calculation of r droop . over-voltage protection the FAN5094 constantly monitors the output voltage for protection against over-voltage conditions. if the voltage at the vfb pin exceeds 2.2v, an over-voltage condition is assumed and the FAN5094 latches on the external low-side mosfet and latches off the high-side mosfet. the dc-dc converter returns to normal operation only after v cc has been recycled. thermal design considerations because of the very large gate capacitances that the FAN5094 may be driving, the ic may dissipate substantial power. it is important to provide a path for the ics heat to be removed, to avoid overheating. in practice, this means that each of the pins should be connected to as large a trace as possible. use of the heavier weights of copper on the pcb is also desirable. since the mosfets also generate a lot of heat, efforts should be made to thermally isolate them from the ic. over temperature protection if the FAN5094 die temperature exceeds approximately 150 c, the ic shuts itself off. it remains off until the temper- ature has dropped approximately 25 c, at which time it resumes normal operation. component selection mosfet selection this application requires n-channel enhancement mode field effect transistors. desired characteristics are as follows: low drain-source on-resistance, ? ds,on < 10m ? (lower is better); power package with low thermal resistance; drain-source voltage rating > 15v; low gate charge, especially for higher frequency operation. for the low-side mosfet, the on-resistance (r ds,on ) is the primary parameter for selection. because of the small duty cycle of the high-side, the on-resistance determines the power dissipation in the low-side mosfet and therefore signi?antly affects the ef?iency of the dc-dc converter. for high current applications, it may be necessary to use two mosfets in parallel for the low-side for each phase. c t10 a ? 1v out + --------------------- - = rt ? () 50 10 ? 9 fhz () --------------------- - = r droop ? () 2n ? v ? droop rt ? i max r ds on , ? -------------------------------------------------- - =
FAN5094 product specification 18 rev. 1.0.2 5/13/02 for the high-side mosfet, the gate charge is as important as the on-resistance, especially with a 12v input and with higher switching frequencies. this is because the speed of the transition greatly affects the power dissipation. it may be a good trade-off to select a mosfet with a somewhat higher r ds,on , if by so doing a much smaller gate charge is available. for high current applications, it may be necessary to use two mosfets in parallel for the high-side for each phase. at the FAN5094s highest operating frequencies, it may be necessary to limit the total gate charge of both the high-side and low-side mosfets together, to avert excess power dis- sipation in the ic. for details and a spreadsheet on mosfet selection, refer to applications bulletin ab-8. gate resistors use of a gate resistor on every mosfet is mandatory. the gate resistor prevents high-frequency oscillations caused by the trace inductance ringing with the mosfet gate capacitance. the gate resistors should be located physically as close to the mosfet gate as possible. the gate resistor also limits the power dissipation inside the ic, which could otherwise be a limiting factor on the switch- ing frequency. it may thus carry signi?ant power, especially at higher frequencies. as an example, consider the gate resistors used for the low-side mosfets (q2 and q4) in figure 1. the fdb7045l has a maximum gate charge of 70nc at 5v, and an input capacitance of 5.4nf. the total energy used in powering the gate during one cycle is the energy needed to get it up to 5v, plus the energy to get it up to 12v: this power is dissipated every cycle, and is divided between the internal resistance of the FAN5094 gate driver and the gate resistor. thus, and each gate resistor thus requires a 1/4w resistor to ensure worst case power dissipation. the same calculation may be performed for the high-side mosfets, bearing in mind that their gate voltage swings only the charge pump voltage of 5v. inductor selection choosing the value of the inductor is a tradeoff between allowable ripple voltage and required transient response. a smaller inductor produces greater ripple while producing better transient response. in any case, the minimum induc- tance is determined by the allowable ripple. the ?st order equation (close approximation) for minimum inductance for a two-phase converter is: where: vin = input power supply vout = output voltage f = dc/dc converter switching frequency esr = equivalent series resistance of all output capacitors in parallel vripple = maximum peak to peak output ripple voltage budget. one other limitation on the minimum size of the inductor is caused by the current feedback loop stability criterion. the inductor must be greater than: where l is the inductance in henries, r ds,on is the on-state resistance of one phases low-side mosfet, r droop is the value of the droop resistor in ohms, v in is either 5v or 12v, and v o is the output voltage. for most applications, this for- mula will not present any limitation on the selection of the inductor value. a typical value for the inductor is 1.3 h at an oscillator frequency of 1.2mhz (300khz each phase) and 220nh at an oscillator frequency of 4mhz (1mhz each phase). for other frequencies, use the interpolating formula schottky diode selection the application circuits of figures 1-2 show a schottky diode, d1 (d2 respectively), one in each phase. they are used as free-wheeling diodes to ensure that the body-diodes in the low-side mosfets do not conduct when the upper mosfet is turning off and the lower mosfets are turning on. it is undesirable for this diode to conduct because its high forward voltage drop and long reverse recovery time degrades ef?iency, and so the schottky provides a shunt path for the current. since this time duration is extremely short, being minimized by the adaptive gate delay, the selec- tion criterion for the diode is that the forward voltage of the schottky at the output current should be less than the forward eqv 1 2 -- - c + ? v 2 ? 70nc 5v 1 2 -- - + ? 5.4nf 12v 5v () 2 ? == 482nj = p rgate efr gate ? ? r gate r internal + () ------------------------------------------------ - 482nj 300khz ? == 4.7 ? 4.7 ? 1.0 ? + -------------------------------- - 19mw = ? l min v in 2v ? out f ---------------------------------- - v out v in ----------- esr v ripple ----------------- ? ? = l310 10 ? r ds on , r droop v in 2v o () ? ? ? lnh () 1.86 10 6 fkhz () --------------------------- 240
product specification FAN5094 rev. 1.0.2 5/13/02 19 voltage of the mosfets body diode. power capability is not a criterion for this device, as its dissipation is very small. output filter capacitors the output bulk capacitors of a converter help determine its output ripple voltage and its transient response. it has already been seen in the section on selecting an inductor that the esr helps set the minimum inductance. for most con- verters, the number of capacitors required is determined by the transient response and the output ripple voltage, and these are determined by the esr and not the capacitance value. that is, in order to achieve the necessary esr to meet the transient and ripple requirements, the capacitance value required is already very large. the most commonly used choice for output bulk capacitors is aluminum electrolytics, because of their low cost and low esr. the only type of aluminum capacitor used should be those that have an esr rated at 100khz. consult application bulletin ab-14 for detailed information on output capacitor selection. for higher frequency applications, particularly those running the FAN5094 oscillator at >1mhz, oscon or ceramic capaci- tors may be considered. they have much smaller esr than comparable electrolytics, but also much smaller capacitance. the output capacitance should also include a number of small value ceramic capacitors placed as close as possible to the processor; 0.1? and 0.01? are recommended values. input filter the dc-dc converter design may include an input inductor between the system main supply and the converter input as shown in figure 5. this inductor serves to isolate the main supply from the noise in the switching portion of the dc-dc converter, and to limit the inrush current into the input capac- itors during power up. a value of 1.3? is recommended. it is necessary to have some low esr capacitors at the input to the converter. these capacitors deliver current when the high side mosfet switches on. because of the interleaving, the number of such capacitors required is greatly reduced from that required for a single-phase buck converter. figure 5 shows 3 x 1000 f, but the exact number required will vary with the output voltage and current, according to the formula for the four phase FAN5094, where dc is the duty cycle, dc = vout / vin. capacitor ripple current rating is a function of temperature, and so the manufacturer should be contacted to ?d out the ripple current rating at the expected opera- tional temperature. for details on the design of an input ?ter, refer to applications bulletin ab-16. figure 5. input filter design considerations and component selection additional information on design and component selection may be found in fairchilds application note 59. i rms i out 4 -------- - 4dc 16dc 2 = 1.3 h +12v 1000 f, 16v electrolytic vin
FAN5094 product specification 20 rev. 1.0.2 5/13/02 pcb layout guidelines placement of the mosfets relative to the FAN5094 is critical. place the mosfets such that the trace length of the hidrv and lodrv pins of the FAN5094 to the fet gates is minimized. a long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the fet. this noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very dif?ult to suppress. in general, all of the noisy switching lines should be kept away from the quiet analog section of the FAN5094. that is, traces that connect to pins 9-20 (ldrv, hdrv, gnd and boot) should be kept far away from the traces that connect to pins 1 through 8, and pins 21-28. place the 0.1? decoupling capacitors as close to the FAN5094 pins as possible. extra lead length on these reduces their ability to suppress noise. each power and ground pin should have its own via to the appropriate plane. this helps provide isolation between pins. place the mosfets, inductor, and schottky of a given phase as close together as possible for the same reasons as in the ?st bullet above. place the input bulk capacitors as close to the drains of the high side mosfets as possible. in addition, placement of a 0.1 f decoupling cap right on the drain of each high side mosfet helps to suppress some of the high frequency switching noise on the input of the dc-dc converter. place the output bulk capacitors as close to the cpu as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. additional space between the output capacitors and the cpu will allow the parasitic resistance of the board traces to degrade the dc-dc converters performance under severe load transient conditions, causing higher voltage deviation. for more detailed information regarding capacitor placement, refer to application bulletin ab-5. a pc board layout checklist is available from fairchild applications. ask for application bulletin ab-11. pc motherboard sample layout and gerber file a reference design for motherboard implementation of the FAN5094 along with the pcad layout gerber ?e and silk screen can be obtained through your local fairchild represen- tative. FAN5094 evaluation board fairchild provides an evaluation board to verify the system level performance of the FAN5094. it serves as a guide to performance expectations when using the supplied external components and pcb layout. please contact your local fairchild representative for an evaluation board. additional information for additional information contact your local fairchild representative.
product specification FAN5094 rev. 1.0.2 5/13/02 21 mechanical dimension 28 lead tssop a .047 1.20 symbol inches min. max. min. max. millimeters notes a1 .002 .006 0.05 0.15 .012 0.30 b .007 0.19 c .008 .013 0.09 0.20 e .172 .180 4.30 4.50 .018 .030 0.45 0.75 .026 bsc 0.65 bsc e .252 bsc 6.40 bsc h l 0 8 0 8 3 5 2 2 n28 28 ccc .004 0.10 d .378 .386 9.60 9.80 notes: 1. 2. 3. 4. 5. dimensioning and tolerancing per ansi y14.5m-1982. "d" and "e" do not include mold flash. mold flash or protrusions shall not exceed .010 inch (0.25mm). "l" is the length of terminal for soldering to a substrate. terminal numbers are shown for reference only. symbol "n" is the maximum number of terminals. h e a d e b a1 c ccc c lead coplanarity seating plane l c
FAN5094 product specification 5/13/02 0.0m 001 stock#ds30005094 ? 200 fairchild semiconductor corporation life support policy fairchild s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. ordering information product number package FAN5094mtc 28 pin tssop FAN5094mtcx tape & reel

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